L&T Semiconductor Technologies | Physical Verification Engineer

3 weeks ago


Delhi, India L&T Semiconductor Technologies Full time
Description:

This position is for a senior-level physical verification engineer who will work on Physical verification of a complex SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/IP/Blocks.Experience:Expertise in physical verification of SoC/Full-chip-level and/or block-level DRC, Experience and understanding of all phases of the IC design process from RTL->GDS2LVS, ERC/PERC, DFM, OPC, Tapeout processPreferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundriesExperience in developing sign-off methodology/flow to and supporting a larger teamExperience in debugging LVS issues at chip-level with complex analog-mixed signal IPsExperience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip componentsGood understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc.Experience with ERC rules, PERC rules, ESD rules has an added advantageExpert in EDA Tools: Mentor (Calibre), Synopsys (ICV)/ Cadence (Pegasus)Strong communication skills, problem solving and analytical skills

Qualification: BTECH/ MTECH with 5 - 15Years of Experience

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