Analog Layout Engineer
2 weeks ago
Harnessing the engineering mastery of L&T, LTSCT is forging a path to a world-class semiconductor ecosystem rooted in India. We aim to rewrite the rules of cutting-edge technology through relentless innovation to foster a vibrant culture of ingenuity, fuelling progress on every chip.
We have a presence in four prominent geographies i.e. US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai.
Job Description:LTSCT’s Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards.
Areas of Responsibilities:Responsibilities include creating the physical layout of analog circuits on semiconductor chips. This involves translating circuit designs into physical layouts that meet performance, area, and power specifications.The main responsibility will be to design layout designs for Analog blocks IP.
Engagement and collaboration across global sites is a key aspect of this role. Strong technical, communication, and consensus building skills will be required as well as must. The ideal candidate will partner with local and global SoC teams to drive best practices with a target of productivity improvement.
• Experience in Mixed-Signal layout design, holding bachelor’s degree in electrical/Electronic Engineering.• To work independently on block levels analog layout design from schematic, estimating the Area,Optimizing Floorplan, Routing and Verifications.Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,• Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5nm FinFet and below.• Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.• Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must.• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,• Ability to understand design constraints and implement high-quality layouts.• Multiple Tape out support experience will be an added advantage.• Good people skills and critical thinking abilities to resolve the issue technically, and professionally.• Excellent communication. Responsible for timely execution with high quality of layout design.
Primary Skills• Analog Layout• Process or technology experience: TSMC/GF – 7nm, 5nm, 10nm,28nm , 55nm, BCD Process• EDA Tools:• Layout Editor: Cadence Virtuoso L, XL• Physical verification : DRC, LVS, Calibre• Design Analog IP Layout design in advanced node (2nm/3nm/5nm) processes and
High voltage BCD
processes• Must have high expertise in CMOS / Bi-CMOS /
SOI
/ FinFET processes
Qualification:Degree in Electronics Engineering or Electrical Engineering with 2+ years to 5 years of experience on analog/mixed signal layout design. Master’s or PhD degree in the area of Electronics or electrical engineering from a reputed university will be an added advantageGood knowledge in physical verification such as LVS, DRC, AntennaMust know the parasitic extraction and know how to fix itExcellent written and verbal communication skill.Must have worked on complex, multi-hierarchy layout design with extensive interconnects.Must know the working experience in version control flowMust have strong track record of several successful tapeouts.
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