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Senior Design Verification Engineer
1 month ago
We are looking for talented DV engineers to expand our team at L&T Technology Services. Our team focuses on delivering high-quality designs and we need your expertise in VLSI skills, particularly in SV/UVM.
Job DescriptionIn this role, you will be responsible for developing coverage models and performing analysis for the PCIE Physical & Data Link Layer protocol. Additionally, you will participate in regression failure triage and testbench bug fixes. You may also be involved in integrating qualification of subunit design/models and VIP in unit DV environment.
Requirements- Strong experience in SV/UVM
- Knowledge of PCIE protocol is a plus
We offer a competitive salary package that includes a base salary of $120,000 per year, depending on location. In addition to your salary, you will receive comprehensive benefits, including medical, dental, and vision insurance, 401(k) matching, and paid time off.
L&T Technology Services is an equal opportunity employer and welcomes applications from diverse candidates. We are committed to creating an inclusive work environment where everyone has the opportunity to thrive.
