Jones RecruitZo | Senior STA Engineer | bangalore

4 days ago

Bengaluru, India Jones RecruitZo Full time
Job Description (JD): Senior STA EngineerPosition:

Senior Static Timing Analysis (STA) EngineerLocations:

Bengaluru and Hyderabad, IndiaExperience:

5+ yearsDepartment:

VLSI/IC DesignJob Type:

Full-timeCompany Overview:We are a leading global provider of advanced semiconductor solutions, specializing in designing cutting-edge ICs. We are looking for a highly skilled and experienced

Senior STA Engineer

to join our team in either

Bengaluru or Hyderabad . This is a fantastic opportunity to work on state-of-the-art designs and be part of a highly skilled engineering team focused on high-performance IC development.Job Summary:The Senior STA Engineer will be responsible for leading the static timing analysis and closure efforts for complex digital designs, both at the block level and SoC level. This role requires extensive experience with timing analysis, timing signoff tools, and working with multiple teams (design, implementation, and physical design) to ensure that timing constraints are met, and critical paths are closed efficiently.Key Responsibilities:Timing Analysis:

Perform static timing analysis (STA) at both the block and SoC levels to ensure that timing constraints are met across multiple operating conditions and corners.Constraint Development:

Work with design and implementation teams to develop, define, and qualify timing constraints (SDC and constraint syntax) to ensure timing closure.Industry Tools Expertise:

Utilize industry-standard STA tools such as

Primetime

and

Tempus

for analysis and signoff. Experience with

DMSA

or

Tweaker

is a must.Timing Closure:

Drive timing closure at both block and full-chip levels, including complex timing paths, multi-voltage designs, and advanced process nodes (7nm, 5nm, etc.).MMMC & Timing Modes:

Expertise in

MMMC

(Multi-Mode Multi-Corner) analysis and handling different timing modes and corners effectively.Collaboration:

Work closely with physical design engineers to resolve timing-related issues, such as timing violations, noise, and crosstalk delays, during implementation.Timing ECO Generation:

Generate and manage

Timing ECOs

(Engineering Change Orders) for multi-voltage designs to meet timing and noise requirements.Timing & Noise Signoff:

Own the

timing and noise signoff closure

process at both block-level and full-chip-level, ensuring signoff criteria are met under various scenarios.Crosstalk & Timing Derates:

Ensure a clear understanding of crosstalk delay/noise,

AOCV/POCV

concepts, and how they impact timing closure.Scripting & Automation:

Develop and optimize

TCL/Perl

scripts to automate tasks and improve efficiency in STA processes.Tracking & Reporting:

Plan and track self-execution, report progress regularly, and document results in a systematic and organized manner.Skills & Experience:Experience:

8+ years of experience in

Static Timing Analysis (STA)

for digital VLSI/IC designs, with expertise in both

block-level and SoC-level

timing analysis.Tools Expertise:

Proficiency with STA tools such as

Primetime ,

Tempus ,

DMSA ,

Tweaker , or equivalent tools.Constraint Syntax:

Strong understanding of

SDC (Synopsys Design Constraints)

and timing constraint syntax.Timing Closure:

Proven experience in achieving timing closure for complex designs, including multi-voltage designs and advanced process nodes (e.g., 7nm, 5nm).Multi-Mode Multi-Corner (MMMC):

Expertise in

MMMC

analysis and handling different timing modes and process corners.Crosstalk & Noise:

Good understanding of

crosstalk delay ,

timing derates ,

AOCV/POCV

concepts, and their impact on timing closure.ECOs:

Experience in

Timing ECO generation

and managing timing adjustments for multi-voltage designs.Collaboration:

Experience working closely with

physical design engineers

to resolve timing-related issues during implementation and layout.Scripting Skills:

Proficiency in

TCL

and/or

Perl

scripting for automation and customization of STA flows.Advanced Process Nodes:

Experience with

advanced process nodes

(e.g., 7nm, 5nm) and their associated timing challenges.Problem Solving:

Excellent analytical and problem-solving skills for closing difficult timing paths manually and efficiently.Educational Qualification:

Bachelor's or Master’s degree in

Electrical Engineering ,

VLSI , or related fields.Preferred Skills:Familiarity with

low-power design techniques

and their impact on STA.Experience with

clock domain crossing (CDC)

and managing related issues.Knowledge of

timing derates

and their impact on timing closure.

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