Rtl Engineer
5 days ago
Role 1: Sr. RTL Synthesis Engineer Parent company : TEKsystems Client/ Domain: Semiconductor Manufacturing Notice Period Expectations : Immediate to 45 days Work Location (client): Hitec city, Hyderabad Work timings: Normal Working hours Qualification :Bachelors Degree / MS or equivalent work experience in Electrical Engineering or similar technology area. Experience : 3+ Years Skills required 1.RTL Coding (Verilog/ Sys Verilog) at least intermediate Proficiency 2.Solving timing Constraints and STA. 3.Proficiency in Digital Electronics Design concepts 4.Proficiency in FPGA design flow and vivado. 5.Previous Exposure to AMD Products is an Added advantage Basic Job Deliverable | RTL synthesis 1.Contribute to triaging reported issues in several Vivado product areas, such as design entry, synthesis, implementation, and help engineering address them effectively . 2.Actively explore innovative methodologies and their impact on flow and design practices, with emphasis on timing closure and compile time, as well as productivity with the new Versal ACAP family. Functional Skills 3.Develop and deliver training materials on new features and methodologies. Stay current with and propose the internal use of industry approaches, algorithms, and practices. Interview Process ( 2 Levels) 1.Technical round (panel of 3, Areas covered Verilog/Sys Verilog, Digital Design, Timing Constraints/analysis, STA, FPGA Flow. 2.Techno managerial, Understanding Role fitment and exploring possible areas you could contribute to team ………………………………………………………………………………………………………… Role 2 : RTL FPGA Engineer Parent company : TEKsystems Client/ Domain: Semiconductor Design/Manufacturing Work Location (client): Hitec city, Hyderabad Work timings: Normal Working hours Qualification : BTech/MTech Experience Level : 3+ years Required skill for the Job | RTL FPGA Engineer -New IP Design or existing IP Design role, -RTL Coding IP Design/ Verification/ integration -Timing analysis, STA along with tools like Vivado . -Experience on FPGA platforms like AMD(XILINX)/Altera. -Expertise in digital hardware designing using Verilog on large AMD(Xilinx)/altera FPGAs -Experience in scripting language like perl, python and tcl -Working experience on Linux. -Ensure to complete design and timing verification tasks within allotted timelines. -Ability to work individually and in a team. Basic Job Deliverable: 1.Design, implementation, test, integration, and delivery of system level digital designs for FPGA blocks timing verification 2.Perform task of debugging design timing related issues on different FPGA families 3.Perform the work of manifold segmentation of the FPGA designs. 4.Run internal scripts for performance testing and update scripts when necessary ……………………………………………………………………………………………………… Join Silicon Circle LinkedIn Group ⚡️ A trusted circle for professionals across the semiconductor industry — from RTL and DV to physical design, DFT, validation, analog, and more. Share career opportunities, insights, and learning resources
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Engineer - RTL
6 days ago
Hyderabad, Telangana, India Quest Global Full time ₹ 5,00,000 - ₹ 15,00,000 per yearJob Requirements he RTL Design Engineer is responsible for designing and implementing digital circuits using Hardware Description Languages (HDL) such as Verilog or VHDL.They work on creating logic at the Register Transfer Level (RTL) and collaborate with verification, synthesis, and physical design teams.Key Responsibilities:Understand and analyze design...
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RTL Design Engineer
2 days ago
Hyderabad, Telangana, India ACL Digital Full time ₹ 4,00,000 - ₹ 12,00,000 per yearRTL Design EngineerSkill: ASIC RTL Design with LINT, CDC. Experience: 1 to 3 Years Notice Period: Immediate to 15 days Share your updated resume now.
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Rtl design engineer
6 days ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 4+ yrsLoctaion: HyderabadJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• So C & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...
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Rtl design engineer
5 days ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 4+ yrsLoctaion: HyderabadJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• So C & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...
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RTL Design Engineer
3 weeks ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 4+ yrsLoctaion: HyderabadJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• SoC & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...
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RTL Design Engineer
3 weeks ago
Hyderabad, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 4+ yrsLoctaion: Hyderabad /BangaloreJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• SoC & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL quality...
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RTL Design Engineer
6 days ago
Hyderabad, India ACL Digital Full timeJob Title - RTL Design Engineers Exp Level: 4+ yrsLoctaion: Hyderabad /BangaloreJob Description:• RTL coding knowledge• Top-level (SOC) level basic industry standard Arch knowledge• SoC & IP level Integration knowledge• IPXACT knowledge• IORING and Phys & GPIOs basic functionality• Design Partitioning(Tilification) knowledge• Design RTL...
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RTL Design Engineer
3 weeks ago
Hyderabad, India ACL Digital Full timePosition: RTL Design Engineer Experience: 5 - 8 Years Qualifications: BE/Btech in ECE/EEE Responsibilities - The candidate should have strong RTL design experience. Strong design experience in Ethernet IPs or Ethernet protocol domain. Knowledge in Verilog/VHDL languages Scripting languages: TCL/Perl/Python (any one). Knowledge of AXI Protocols.
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RTL Design Engineer
2 weeks ago
Hyderabad, India ACL Digital Full timePosition: RTL Design Engineer Experience: 5 - 8 Years Qualifications: BE/Btech in ECE/EEE Responsibilities - The candidate should have strong RTL design experience. Strong design experience in Ethernet IPs or Ethernet protocol domain. Knowledge in Verilog/VHDL languages Scripting languages: TCL/Perl/Python (any one). Knowledge of AXI Protocols.
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RTL Design Engineer
1 week ago
Hyderabad, India ACL Digital Full timePosition: RTL Design Engineer Experience: 5 - 8 Years Qualifications: BE/Btech in ECE/EEE Responsibilities - - The candidate should have strong RTL design experience. - Strong design experience in Ethernet IPs or Ethernet protocol domain. - Knowledge in Verilog/VHDL languages - Scripting languages: TCL/Perl/Python (any one). - Knowledge of AXI Protocols.
