Physical verification engineer

1 week ago


Bengaluru, India ACL Digital Full time

Job Title: Physical Verification EngineerExperience: 4+Years Location: Banglaore Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design / FoundryJob Summary:We are looking for a Physical Verification Engineer with strong expertise in physical verification flows to ensure that layouts are signoff-clean and compliant with foundry process design rules. The ideal candidate will be responsible for DRC, LVS, ERC, Antenna, and other checks across block-level and full-chip designs using industry-standard EDA tools.Key Responsibilities:Own and execute block-level and full-chip DRC, LVS, ERC, Antenna, and Density checks.Analyze physical verification violations and debug layout/schematic mismatches.Work closely with layout, circuit design, and digital backend teams to ensure verification closure.Develop and maintain PV rule decks (if applicable) and flows.Interface with foundries (e.g., TSMC, Samsung, Global Foundries) for rule interpretation and deck issues.Support tapeout preparation and signoff activities.Automate PV flows and improve runtime efficiency through scripting.Contribute to PV methodology development and cross-functional training.Required Skills and Experience:B. E/B. Tech or M. E/M. Tech in Electronics, Electrical, or VLSI Design.4+years of hands-on experience in physical verification.Strong experience with Calibre (Mentor/Siemens) or Assura/PVS (Cadence) for DRC/LVS/ERC.Familiarity with GDSII/OASIS layout formats and layout hierarchy handling.Knowledge of layout design principles and basic CMOS concepts.Good debugging and analytical skills.Scripting knowledge in Tcl, Python, or Perl for flow automation.Preferred Qualifications:Experience working at advanced technology nodes (7nm, 5nm, 3nm).Exposure to full-chip integration and signoff tapeouts.Familiarity with foundry PV rule decks and process guidelines.Knowledge of electromigration (EM), IR drop, or DFM checks is a plus.Interested can share Cv to



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