
Physical Verification lead
3 weeks ago
JOB Descrition
- Take the leadership role of developing and supporting block and full chip automated physical verification flows and scripts
- Strong fundamentals in physical design verification using Calibre tool.
- Strong experience in multi voltage domain and design experience with multi-million instances.
- Work with the PD team to clean up all DRC/LVS/ESD/ERC/ANT violations and sign off PV for tapeouts
- Experience of working in lower geometries(FinFets) is preferred. Experience is TSMC5nm, TSMC4nm is a plus.
- Automation of DesignREV using TCL scripting is a must.
- Familiarity of PnR flows and tools such as Cadence Innovus is must.
- Knowledge and hands on virtuoso experience is plus.
- Experience in power gating digital designs is a plus.
- Excellent verbal and written communication skills are required.
- Perform block and full-chip physical verification and work with the physical design team to close design issues
- Experience level : 7+ years
Minimum Requirement:
- Bachelor's/Masters' degree in electrical engineering, computer engineering, or computer science
- 7+ years of experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support
- Experience in industry-standard physical verification EDA tools
- Experience in ASIC physical design and custom circuit design
- Proficiency in writing Linux shell scripts in Perl, TCL, and Python
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