Memory Layout Engineer

ACL Digital is looking for a1.Memory Layout Engineer with 2+ years of Exp for Noida2.Memory Design Engineer with 2+ years of Exp for NoidaInterested share cv to

ACL Digital is looking for a1.Memory Layout Engineer with 2+ years of Exp for Noida2.Memory Design Engineer with 2+ years of Exp for NoidaInterested share cv to

ACL Digital is looking for a 1.Memory Layout Engineer with 2+ years of Exp for Noida 2.Memory Design Engineer with 2+ years of Exp for Noida Interested share cv to

- Experience : 3 to 8 years- Location : Hyderabad/NoidaRole and Responsibilities:- Responsible for Memory Compiler layout development and verification.·- Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·- Perform layout verification like LVS/ DRC/...

Experience : 3 to 8 yearsLocation : Hyderabad/NoidaRole and Responsibilities:Responsible for Memory Compiler layout development and verification.·Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·Perform layout verification like LVS/ DRC/ Latchup,...

ACL Digital is looking for a1.Memory Layout Engineer with 2+ years of Exp for Noida2.Memory Design Engineer with 2+ years of Exp for NoidaInterested share cv to karthick.v@acldigital.com

Memory Layout Design: Create and optimize physical layouts for memory components (e.g., SRAM, DRAM, ROM) using advanced EDA tools like Synopsys Custom Compiler or other industry-standard tools. Ensure that the memory design meets specifications for area, power, performance, and manufacturability. Memory Optimization: Work on layout optimizations for area,...

Experience : 3 to 8 yearsLocation : Hyderabad/NoidaRole and Responsibilities: Responsible for Memory Compiler layout development and verification.·Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·Perform layout verification like LVS/ DRC/ Latchup,...

- Experience : 3 to 8 years - Location : Hyderabad/Noida Role and Responsibilities: - Responsible for Memory Compiler layout development and verification.· - Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.· - Perform layout verification like LVS/ DRC/...

General Summary:Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies...