Memory Layout Engineer

4 weeks ago

Noida, India ACL Digital Full time

Memory Layout Design: Create and optimize physical layouts for memory components (e.g., SRAM, DRAM, ROM) using advanced EDA tools like Synopsys Custom Compiler or other industry-standard tools. Ensure that the memory design meets specifications for area, power, performance, and manufacturability. Memory Optimization: Work on layout optimizations for area, speed, and power consumption. Collaborate with design and architecture teams to implement memory features that enhance the overall system performance. Design Rule Checks (DRC) & Layout Versus Schematic (LVS): Perform thorough design rule checks (DRC) and layout versus schematic (LVS) checks to ensure that memory layouts comply with foundry design rules and pass all required checks before tape-out.

  • Memory Layout Engineer

    7 days ago

    noida, India ACL Digital Full time

    ACL Digital is looking for a 1.Memory Layout Engineer with 2+ years of Exp for Noida 2.Memory Design Engineer with 2+ years of Exp for Noida Interested share cv to

  • Memory Layout Engineer

    2 days ago

    Noida, India ACL Digital Full time

    ACL Digital is looking for a 1.Memory Layout Engineer with 2+ years of Exp for Noida 2.Memory Design Engineer with 2+ years of Exp for Noida Interested share cv to

  • Memory Layout Engineer

    2 weeks ago

    Noida, India ACL Digital Full time

    ACL Digital is looking for a1.Memory Layout Engineer with 2+ years of Exp for Noida2.Memory Design Engineer with 2+ years of Exp for NoidaInterested share cv to karthick.v@acldigital.com

  • Memory Layout Engineer

    2 weeks ago

    Noida, India ACL Digital Full time

    Experience : 3 to 8 yearsLocation : Hyderabad/NoidaRole and Responsibilities: Responsible for Memory Compiler layout development and verification.·Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·Perform layout verification like LVS/ DRC/ Latchup,...

  • Memory Layout Engineer

    1 week ago

    Noida, India ACL Digital Full time

    Experience : 3 to 8 yearsLocation : Hyderabad/NoidaRole and Responsibilities: Responsible for Memory Compiler layout development and verification.·Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·Perform layout verification like LVS/ DRC/ Latchup,...

  • Memory Layout Engineer

    2 weeks ago

    Noida, India ACL Digital Full time

    Experience : 3 to 8 yearsLocation : Hyderabad/NoidaRole and Responsibilities: Responsible for Memory Compiler layout development and verification.·Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·Perform layout verification like LVS/ DRC/ Latchup,...

  • Memory Layout Engineer

    3 weeks ago

    Noida, India ACL Digital Full time

    ACL Digital is looking for a 1.Memory Layout Engineer with 2+ years of Exp for Noida 2.Memory Design Engineer with 2+ years of Exp for Noida Interested share cv to karthick.v@acldigital.com

  • Memory Layout Engineer

    3 weeks ago

    Noida, India ACL Digital Full time

    - Experience : 3 to 8 years - Location : Hyderabad/Noida Role and Responsibilities: - Responsible for Memory Compiler layout development and verification.· - Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.· - Perform layout verification like LVS/ DRC/...

  • Memory Layout Engineer

    3 weeks ago

    Noida, India ACL Digital Full time

    Experience : 3 to 8 years Location : Hyderabad/Noida Role and Responsibilities: Responsible for Memory Compiler layout development and verification.· Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.· Perform layout verification like LVS/ DRC/ Latchup,...

  • Memory Layout Engineer

    2 weeks ago

    Noida, Uttar Pradesh, India, Ghaziabad ACL Digital Full time

    Experience : 3 to 8 yearsLocation : Hyderabad/NoidaRole and Responsibilities: Responsible for Memory Compiler layout development and verification.·Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·Perform layout verification like LVS/ DRC/ Latchup,...