
Memory Layout Engineer
23 hours ago
- Experience : 3 to 8 years
- Location : Hyderabad/Noida
Role and Responsibilities:
- Responsible for Memory Compiler layout development and verification.·
- Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·
- Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation.· Responsible for on-time delivery of block-level layouts with acceptable quality.· Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.·
- Guide junior team-members in their execution of Sub block-level layouts & review their work.·
- Contribute to effective project-management.·
- Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.
Qualification/ Requirements:
- Should be well familiar with various levels of memory layouts from custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, decoders.·
- Should have expertise in floor planning, power planning, block area estimation of memory designs or compliers.·
- Should be able to perform leaf cell layout development and physical verification.·
- Should have adequate knowledge of schematics, interface with circuit designer and CAD and process development team.·
- Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.·
- Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,· Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.·
- Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.·
- Should have leadership qualities and able to do multi-tasking as required.·
- Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.·
- Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
- Knowledge of Skill coding and layout automation is a plus.
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Memory Layout Engineer
2 weeks ago
Noida, India ACL Digital Full timeACL Digital is looking for a1.Memory Layout Engineer with 2+ years of Exp for Noida2.Memory Design Engineer with 2+ years of Exp for NoidaInterested share cv to
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Memory Layout Engineer
2 weeks ago
Noida, India ACL Digital Full timeACL Digital is looking for a1.Memory Layout Engineer with 2+ years of Exp for Noida2.Memory Design Engineer with 2+ years of Exp for NoidaInterested share cv to
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Memory Layout Engineer
3 days ago
Noida, India ACL Digital Full timeACL Digital is looking for a 1.Memory Layout Engineer with 2+ years of Exp for Noida 2.Memory Design Engineer with 2+ years of Exp for Noida Interested share cv to
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Noida, India ACL Digital Full time- Experience : 3 to 8 years- Location : Hyderabad/NoidaRole and Responsibilities:- Responsible for Memory Compiler layout development and verification.·- Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·- Perform layout verification like LVS/ DRC/...
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Noida, India ACL Digital Full timeACL Digital is looking for a1.Memory Layout Engineer with 2+ years of Exp for Noida2.Memory Design Engineer with 2+ years of Exp for NoidaInterested share cv to karthick.v@acldigital.com
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