Senior ASIC RTL SOC Lead

Wipro Hiring Senior ASIC/SoC RTL Lead/Manager with 4-18 Yrs of Experience!ℹ️ About the Role:- Require expertise in SoC subsystem/IP design- Must have in-depth knowledge of RTL quality checks (Lint, CDC)- Good understanding of AMBA bus protocols is essential- Knowledge in interface protocols like PCIe, DDR, Ethernet, and more is a plus- Proficiency in...

Wipro Hiring Senior ASIC/SoC RTL Lead/Manager with 4-18 Yrs of Experience!ℹ️ About the Role:- Require expertise in SoC subsystem/IP design- Must have in-depth knowledge of RTL quality checks (Lint, CDC)- Good understanding of AMBA bus protocols is essential- Knowledge in interface protocols like PCIe, DDR, Ethernet, and more is a plus- Proficiency in...

About the Company:Hi All,Greetings from Wipro...!We are Hiring Senior ASIC/SoC RTL Leads/Managers with ~5-20 years of experience to join our Wipro team!About the Role:Expertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge...

About the RoleWipro is seeking a Senior ASIC/SoC RTL Design Specialist to lead our team with 4-18 years of experience.Key Responsibilities:Design and develop complex SoC subsystems and IPsImplement RTL quality checks (Lint, CDC) and ensure high-quality designFamiliarize yourself with AMBA bus protocols and interface protocols like PCIe, DDR, Ethernet, and...

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)Exp 4-15yrsLocation :Bengaluru, Hyderabad, Pune, Noida, Kochi1) Expertise in SoC subsystem/IP design2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog3) In depth knowledge on RTL quality checks (Lint, CDC)4)...

Seeking a skilled RTL Design Lead/Manager (ASIC):- 6-28 years experience in VLSI RTL IP/Subsystem design- Expertise in SoC Clock, Power IP/Subsystem, BUS/Subsystem, and more. Profound grasp of Digital design principles, especially AMBA SoC BUS protocols like APB, AXI, and AHB.. Crafting micro-architecture and detailed design docs for SoC Subsystem, focusing...

About the Company:Hi All,Greetings from Wipro...!We are Hiring Senior ASIC/SoC RTL Leads/Managers with ~5-20 years of experience to join our Wipro team!About the Role:Expertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge...

Are you passionate about working with a growing company offering cutting-edge engineering design services in VLSI, we'd love to hear from you!Lead Soc Technologies is hiring for ASIC RTL Professionals!Experience: 4 years to 8 yearsLocation: BangaloreNotice Period: Immediate to 30 daysMode of work: HybridClient : ODCRTL microarchitecture,RTL design...

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)Exp 4-15yrsLocation :Bengaluru, Hyderabad, Pune, Noida, Kochi1) Expertise in SoC subsystem/IP design2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog3) In depth knowledge on RTL quality checks (Lint, CDC)4)...

About Wipro:We are a global information technology, consulting and business process services company.Our Senior ASIC/SoC RTL Leads/Managers will work with us to deliver cutting-edge digital circuit solutions.Role Overview:This is a challenging role that requires expertise in SoC subsystem/IP design, IP design, Subsystem/Cluster and SoC level integration...

Seeking a skilled RTL Design Lead/Manager (ASIC) :- 6-28 years experience in VLSI RTL IP/Subsystem design- Expertise in SoC Clock, Power IP/Subsystem, BUS/Subsystem, and more . Profound grasp of Digital design principles, especially AMBA SoC BUS protocols like APB, AXI, and AHB. . Crafting micro-architecture and detailed design docs for SoC Subsystem,...

Job Description:Mirafra Software Technologies Pvt Ltd is seeking an experienced Rtl Design Micro Architect Lead to join our team in Bengaluru. As a key member of our hardware engineering team, you will be responsible for designing and developing advanced ASIC microarchitectures.Responsibilities:Lead the development of ASIC microarchitectures, leveraging...

Seeking a skilled RTL Design Lead/Manager (ASIC):- 6-28 years experience in VLSI RTL IP/Subsystem design- Expertise in SoC Clock, Power IP/Subsystem, BUS/Subsystem, and moreProfound grasp of Digital design principles, especially AMBA SoC BUS protocols like APB, AXI, and AHB.Crafting micro-architecture and detailed design docs for SoC Subsystem, focusing on...

Seeking a skilled RTL Design Lead/Manager (ASIC)🌟𝗝𝗼𝗯 𝗗𝗲𝘀𝗰𝗿𝗶𝗽𝘁𝗶𝗼𝗻:- 6-28 years experience in VLSI RTL IP/Subsystem design- Expertise in SoC Clock, Power IP/Subsystem, BUS/Subsystem, and more𝟏. Profound grasp of Digital design principles, especially AMBA SoC BUS protocols like APB, AXI, and AHB.𝟐. Crafting...

Wipro is seeking an experienced Senior ASIC/SoC RTL Engineer to lead our IP design team. As a key member of our engineering team, you will be responsible for designing and integrating complex digital circuits using Verilog/System Verilog.About the RoleThis challenging role involves expertise in SoC subsystem/IP design, integration, and verification. You will...

About the Position:We are seeking an experienced Senior ASIC/SoC RTL Lead to join our team at Wipro.The ideal candidate will have a strong background in SoC subsystem/IP design, expertise in Verilog/System Verilog, and a deep understanding of RTL quality checks.Additionally, knowledge of synthesis and low power is a plus, as well as a good grasp of AMBA bus...

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)Exp 4-15yrsLocation :Bengaluru, Hyderabad, Pune, Noida, Kochi1) Expertise in SoC subsystem/IP design2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog3) In depth knowledge on RTL quality checks (Lint, CDC)4)...

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)Exp 4-15yrsLocation :Bengaluru, Hyderabad, Pune, Noida, Kochi1) Expertise in SoC subsystem/IP design2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog3) In depth knowledge on RTL quality checks (Lint, CDC)4)...

Hello Everyone!MosChip is seeking an ASIC RTL Design Engineer for positions in Bangalore and Hyderabad. Please review the required skills below and let us know if you are interested in this opportunity.company overviewMosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor &...

Wipro is currently seeking a highly skilled Senior ASIC/SoC Design Expert to join their team.The ideal candidate will have extensive experience in SoC subsystem/IP design and possess a deep understanding of RTL quality checks (Lint, CDC).Key responsibilities include:Developing and implementing high-quality SoC designsLeveraging expertise in AMBA bus...