Design for Testability

3 weeks ago


Bengaluru, India Modernize Chip Solutions Pvt. Ltd Full time

Description:



- Accountable for innovative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level.


- Generate and validate ATPG patterns using simulations.


- Shall Validate the DFT implementation using RTL and Gate level simulation.


- Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation.


- Must have experience with Siemens, Synopsys and/or Cadence Cad tools.


- Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python



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