Fiori Technology Solutions

1 week ago

Bengaluru, India Fiori Technology Solutions Inc Full time

Job Description :We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success.Key Responsibilities : - Own and drive timing closure for multiple blocks or full-chip designs from synthesis through tape-out.- Develop and maintain timing constraints (SDC) for synthesis, place-and-route, and sign-off flows.- Perform setup, hold, recovery, and removal analysis using industry-standard STA tools. - Analyze timing reports and debug violations, providing guidance to physical design, RTL, and DFT teams.- Work closely with clock, power, and signal integrity engineers to address timing and noise-related issues.- Lead STA reviews with design and physical implementation teams, ensuring issues are tracked and resolved.- Collaborate with methodology teams to enhance STA flows and timing sign-off quality.- Contribute to methodology improvements for STA and PNR flows.- Mentor and guide junior engineers in STA and timing-driven PNR techniques.Qualifications : Must-Have : - Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or related field.- 10 - 12 years of hands-on experience in STA for large, complex ASIC/SoC designs.- Proven PNR experience to handle flat SoC designs in Cadence flow. - Solid understanding of multi-mode, multi-corner (MMMC) timing analysis.- Proficiency in timing constraints writing (SDC), clock domain crossing (CDC) considerations, and asynchronous interface analysis.- Experience with ECO timing closure and post-route sign-off.- Prior experience in team leadership or technical mentoring.Nice-to-Have : - Familiarity with scripting languages (Tcl, Perl, Python) for flow automation.- Exposure to low-power design techniques (UPF/CPF).- Knowledge of signal integrity, EM/IR drop impacts on timing.- Experience in the automotive industry is a plus (ref:hirist.tech)

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