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Fiori Technology Solutions
2 weeks ago
Job Description
We are looking for a highly experienced DFT Lead Engineer to take ownership of Design-for-Test (DFT) architecture, implementation, and sign-off for complex flat SoC designs. This role requires deep expertise in PNR (Place-and-Route) within Cadence flow.
Key Responsibilities
- Lead DFT strategy and implementation for flat SoC designs from RTL through tape-out.
- Develop and integrate test architectures including scan insertion, MBIST, LBIST, JTAG, and boundary scan.
- Work closely with the PNR team to ensure DFT structures are timing- and placement-aware.
- Drive test mode constraint creation and ensure compatibility with functional modes.
- Perform gate-level simulations for test logic verification.
- Own ATPG pattern generation and coverage analysis for manufacturing test.
- Lead reviews and mentor junior DFT engineers in best practices.
Qualifications
Must-Have :
- Bachelors or Masters degree in Electrical/Electronics/Computer Engineering or related field.
- 9 - 12 years of hands-on DFT experience in ASIC/SoC projects.
- Proven PNR experience to handle flat SoC designs in Cadence flow
- Strong knowledge of scan insertion, MBIST, LBIST, boundary scan, JTAG, and related standards (IEEE 1149.x).
- Experience with Synopsys DFT Compiler, Tessent, or equivalent DFT tools.
- Good understanding of STA and SDC constraints for test modes.
- Familiarity with ECO flows in post-PNR stages for DFT fixes.
Nice-to-Have
- Automotive semiconductor industry experience
- Proficiency in scripting (Tcl, Perl, Python) for automation.
- Low-power DFT experience with UPF/CPF.
- Exposure to signal integrity considerations for test structures.
- Prior technical leadership or mentoring experience.
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