Fiori Technology Solutions

2 weeks ago


Bengaluru, India Fiori Technology Solutions Inc Full time

About the Role :We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams.Key Responsibilities :- Lead physical design execution for flat SoC projects from RTL handoff through GDSII.- Perform floorplanning, partitioning, power planning, and clock tree synthesis (CTS).- Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools.- Develop and maintain SDC constraints for PNR stages.- Drive physical verification (DRC, LVS, antenna checks) and resolve violations.- Perform congestion analysis and optimization for flat SoC designs.- Work with methodology teams to improve PNR flow and scalability.- Mentor junior engineers on PNR best practices and advanced Cadence Innovus :- Bachelors or Masters degree in electrical/Electronics/Computer Engineering or related field.- 10- 12 years of hands-on physical design and PNR experience.- Proven ability to handle flat SoC designs in Cadence flow - Strong knowledge of floor planning, CTS, routing, optimization, and sign-off closure.- Solid understanding of STA, SDC creation, and ECO flows for physical implementation.- Prior technical leadership or mentoring :- Automotive semiconductor experience - Low-power implementation (UPF/CPF).- Experience with scripting (Tcl, Perl, Python) for automation. (ref:hirist.tech)



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