Manager - Memory/IP Design Engineering

4 days ago


Bengaluru, India NextJobHunt Full time

Description :Manager - Memory IP Design Engineer (eFuse / MTPM / OTP / MRAM / SRAM)Location : Bangalore, IndiaEmployment Type : Full-timeAbout the Role :We are seeking a highly motivated and experienced Manager - Memory IP Design Engineer to lead our Memory IP team. The ideal candidate will bring deep expertise in custom memory circuit design and a passion for driving innovation in semiconductor technology. You will collaborate closely with cross-functional teams across design, layout, technology, test, and product engineering to deliver high-quality memory IP solutions with minimal cycle time.Key Responsibilities :- Lead and perform circuit design, simulation, and characterization of full custom memory circuits.- Conduct functional simulations and statistical analysis to ensure design robustness and reliability.- Manage IP validation and sign-off through dedicated test chips and silicon bring-up.- Support silicon characterization and post-silicon debug activities.- Collaborate with design and layout teams to ensure optimal implementation and performance.- Drive innovation and process improvements in memory IP design flows.- Participate in design and layout reviews, providing technical guidance to the team.Required Qualifications :- M.Tech in Electrical Engineering, VLSI, or Microelectronics from a reputed institution.- 12- 15 years of relevant experience in memory IP or custom circuit design.- Hands-on experience with EDA tools (Cadence, Mentor Graphics, Synopsys) for schematic design and simulations (Virtuoso, Spectre, HSPICE, etc.).- Proven expertise in Non-Volatile Memory (NVM) design, including MTPM, OTP, MRAM, SRAM, or eFlash.- Understanding of timing characterization and Verilog-based verification.- Strong foundation in analog and mixed-signal circuit design concepts.- Proficiency in reliability and statistical analysis of circuits.- Excellent verbal and written communication skills, with the ability to work effectively with cross-functional global teams.Preferred Qualifications :- Familiarity with Bulk, CMOS, and SOI process technologies.- Hands-on experience with state-of-the-art memory or analog design flows.- Programming experience for automation of design flows (Python, Perl, or TCL).- Exposure to advanced technology nodes (45nm, 32nm, 28nm, and below).- Strong analytical and problem-solving abilities.- Experience working in a multidisciplinary, international environment. (ref:hirist.tech)



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