Memory IP Design Engineer
3 days ago
About the Role
We are seeking a highly motivated and experienced Memory IP Design Engineer (Manager level) to join our global semiconductor design team. The ideal candidate will have deep expertise in custom memory design, simulation, and verification, with proven hands-on experience across NVM technologies such as eFuse, MTPM, OTP, MRAM, and SRAM.
You'll collaborate closely with design, layout, technology, test, and product engineering teams to deliver high-quality, high-reliability memory IPs with optimized cycle time and performance.
Key Responsibilities
Lead circuit design, simulation, and characterization of full-custom memory circuits.
Conduct functional simulations, statistical analysis, and timing characterization.
Manage sign-off and release of memory IPs on dedicated validation test chips.
Support silicon bring-up and post-silicon characterization.
Participate in design and layout reviews, ensuring design quality and efficiency.
Drive innovation and continuous improvement in design methodologies.
Collaborate across global, multi-disciplinary teams for successful project execution.
Required Skills & Experience
12–15 years of experience in custom memory IP design (eFuse, MTPM, OTP, MRAM, SRAM, eFlash).
Proficiency in EDA tools (Cadence Virtuoso, Spectre, Synopsys, Mentor Graphics, HSPICE, etc.).
Strong understanding of analog/mixed-signal design, circuit reliability, and statistical analysis.
Familiarity with timing characterization and Verilog modeling (preferred).
Excellent communication, leadership, and cross-functional collaboration skills.
Preferred Qualifications
Experience with Bulk, CMOS, and SOI process technologies (45/32/28nm and below).
Hands-on with advanced memory or analog design flows.
Programming/scripting for design automation (Python, Perl, Tcl).
Strong analytical and problem-solving mindset with innovation-driven approach.
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