Tenstorrent - RISC-V/CPU Lead - System Verilog
9 hours ago
Position : RISC-V CPU Core Testbench Lead
Experience : 9+ Years
Location : As per company discretion
Job Type : Full-time
Job Summary :
Tenstorrent is seeking a highly skilled and experienced RISC-V CPU Core Testbench Lead with 9+ years of relevant industry experience. The ideal candidate will be a hands-on leader responsible for the end-to-end design, development, and maintenance of highly configurable testbench environments for our cutting-edge RISC-V cores and clusters.
This role is central to our verification strategy, requiring deep expertise in SystemVerilog, UVM, and modern C++, as well as a strong understanding of CPU architecture and microarchitectural design. You will collaborate closely with RTL, DV, and tooling teams to build scalable, reusable infrastructure that accelerates the validation of new features and enables rapid root-cause analysis.
Key Responsibilities :
- Lead the design, development, and maintenance of highly configurable testbench environments for RISC-V cores and clusters using a hybrid approach of synthesizable SystemVerilog, UVM, and modern C++.
- Build key testbench components from the ground up, including harnesses, transactors, functional models, and checkers, while developing specialized utilities such as preloaders and trickboxes to support core validation.
- Serve as a key contributor to our custom C++ Verification Methodology (CVM) by applying modern C++ features (e.g., templates, smart pointers) to simplify testbench development, improve maintainability, and ensure cross-platform portability.
- Integrate UVM-based block-level environments into the broader testbench framework to support complex hybrid simulation workflows.
- Ensure testbench portability across a wide range of platforms, from open-source simulators like Verilator to commercial emulation platforms.
- Support the bring-up of new core and cluster features by enabling rapid validation and providing comprehensive debug support.
- Develop and implement advanced debugging tools and automation to accelerate root-cause analysis for failures across both simulation and emulation environments.
- Collaborate closely with RTL, DV, and tooling teams to define reusable infrastructure and scalable test strategies.
Required Skills & Qualifications :
- 9+ years of relevant industry experience in verification, with a Bachelors or Masters degree in Computer Engineering, or a related field.
- Strong proficiency in modern C++ and SystemVerilog, with extensive hands-on experience in building and contributing to verification libraries or testbench infrastructure.
- Deep, hands-on experience with SystemVerilog UVM, including environment construction and integration into larger simulation contexts.
- Proven experience in working with or contributing to custom DV methodologies (e.g., UVM, C++-based frameworks).
- Solid understanding of software engineering principles, including design patterns, multithreaded programming, and coroutines.
- Working knowledge of CPU architectures (RISC-V, ARM, or x86) and key microarchitectural design elements such as pipelines, caches, and MMUs.
- Strong debugging and analytical skills, with the ability to perform root-cause analysis across different layers of abstraction, from software traces to RTL waveforms.
- Self-driven and adaptable, with a strong bias for automation, code reuse, and building scalable infrastructure.
(ref:hirist.tech)
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