RTL Design Engineer

Hi All,Greetings' from Eximietas Design....!We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..!Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC...

Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ years- Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. - Create micro-architecture specs and ensure designs meet performance, power, and area targets. - Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and...

Job Title: RTL Design Engineers Exp Level: 5+ yrs Loctaion: Hyderabad/BangaloreJob Description: • RTL coding knowledge • Top-level (SOC) level basic industry standard Arch knowledge • SoC & IP level Integration knowledge • IPXACT knowledge • IORING and Phys & GPIOs basic functionality • Design Partitioning(Tilification) knowledge • Design RTL...

RTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 YearsJob DescriptionJob Role: Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design...

RTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:- Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. - Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. - Integrate complex subsystems into SoC environments and support...

College education in Electronics Engineering or Computer EngineeringExp- 7-12 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...

Eximietas Hiring:ASIC SOC RTL Micro Architect Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US.Job Description: Eximietas Design is seeking an experienced and highly skilledRTL Micro Architectto join our growing team. As a key contributor, you will play a critical role...

Lead RTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 6 to 9 YearsJob Description6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.Strong Domain Knowledge on RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System...

Lead RTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 6 to 9 YearsJob Description6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.- Strong Domain Knowledge on RTL Design, implementation, and Timing analysis. - Experience with RTL coding using Verilog/VHDL/System...

We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem. You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs.This role is hybrid,...