Principal RTL Engineer
3 weeks ago
Principal RTL Engineer (AI & Multimedia ) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ BangaloreOur pay comprehensively beats "ALL" Semiconductor product players in the Indian market.We are seeking a highly skilled Principal RTL Engineer with strong expertise in VLSI functional RTL and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead RTL efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases.Requirements Experience: 10+ years in functional RTL; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, RTL, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level RTL with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases RTL and system-level scenarios. RTL Expertise: Strong understanding of OOP concepts in RTL. HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior RTL engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and RTL flows.Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case RTL and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC RTL Responsibilities Lead and contribute to feature, core, and subsystem RTL during ASIC design and development phases through RTLnd Gate-Level simulations. Collaborate with the design team to define RTL requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive RTL closure.. Implement and enhance automation flows to improve RTL efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for RTL methodologies, flows, and deliverables.Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com
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Sr RTL Principal Design Engineer
3 weeks ago
New Delhi, India Cadence System Design and Analysis Full time- RTL Design Engineer for Interface Controller IP development team. - Position is based in Bangalore or Noida. - The role would include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence. - The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are...
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Sr RTL Principal Design Engineer
4 weeks ago
New Delhi, India Cadence System Design and Analysis Full timeRTL Design Engineer forInterface Controller IP developmentteam. Position is based inBangaloreor Noida. The role would include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence. The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as...
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Senior RTL engineer
3 weeks ago
New Delhi, India HCLTech Full timeNote: Not accepting applications below 5 years at the momentSenior RTL Design Engineer (5+ years’ experience)Company: HCL TechLocation: Bangalore/Chennai/Hyderabad/Kochi/NoidaNotice - 0-90 daysJob Summary:We are looking for a talented and experienced RTL Design Engineer to join our team and play a key role in the design and development of next-generation...
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Senior RTL engineer
3 weeks ago
New Delhi, India HCLTech Full timeNote: Not accepting applications below 5 years at the moment Senior RTL Design Engineer (5+ years’ experience) Company: HCL Tech Location: Bangalore/Chennai/Hyderabad/Kochi/Noida Notice - 0-90 days Job Summary: We are looking for a talented and experienced RTL Design Engineer to join our team and play a key role in the design and development of...
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RTL Release Principal Design Engineer
3 weeks ago
New Delhi, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer Engineering Exp- 7-12 Yrs - Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc. - Ability to debug existing Verilog/System verilog test cases with little or no help from the designer. - Functional...
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RTL Release Principal Design Engineer
2 weeks ago
New Delhi, India Cadence System Design and Analysis Full timeCollege education in Electronics Engineering or Computer EngineeringExp- 7-12 Yrs- Working knowledge in RTL design flow steps like RTL coding, Simulation, compilation/testbench validation, Synthesis, Timing, DFT,lint, CDC, LEC etc.- Ability to debug existing Verilog/System verilog test cases with little or no help from the designer.- Functional simulation...
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Lead RTL Design Engineer
4 weeks ago
New Delhi, India ACL Digital Full timeLead RTL Design EngineersExperience Level:10+ years of RTL design and development Job Description: Silicon Design Engineer Location: Hyderabad and BangaloreBasic Job Deliverable: Silicon Design Engineer (RTL Design and Development) o Responsible for RTL design and development o Responsible for generating documents, such as requirements specification, design,...
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RTL Design Engineer
2 weeks ago
New Delhi, India ACL Digital Full timeJob Title: RTL Design Engineers Exp Level: 5+ yrs Loctaion: Hyderabad/BangaloreJob Description: • RTL coding knowledge • Top-level (SOC) level basic industry standard Arch knowledge • SoC & IP level Integration knowledge • IPXACT knowledge • IORING and Phys & GPIOs basic functionality • Design Partitioning(Tilification) knowledge • Design RTL...
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RTL Design Engineer
7 hours ago
New Delhi, India ACL Digital Full timeRTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 YearsJob DescriptionJob Role: Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design...
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RTL Microarchitect
8 hours ago
New Delhi, India Baya Systems Full timeJob Title: Microarchitect & RTL Design Engineer Location: Bangalore, IndiaAbout the Role:We are seeking a seasonedMicroarchitect and RTL Design Engineerwith a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutionsKey...