
Design Engineering Architech
1 day ago
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL
- Design and implement RTL for DFT IP incl. POST, IST
- Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification
- Own and maintain, extend, and enhance existing DFT IP like LBIST
We’re doing work that matters. Help us solve what others can’t.
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Design Engineering Architech
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Noida, India Cadence Full timeAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL Design and implement RTL for DFT IP incl. POST, IST Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification Own and maintain,...
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Design Engineering Architech
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ServiceNow Architech
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ServiceNow Architech
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