Senior/Lead STA engineer
3 days ago
We’re Hiring: STA Engineer | 5–15 Years Experience | Bangalore Company:ACL Digital Company Location:Bangalore Experience:5 to 15 Years Job Type:Full-TimeACL Digitalis looking forSenior Static Timing Analysis (STA) Engineerswith solid experience in timing closure of advanced SoC designs. If you’re an STA expert who thrives in fast-paced, technically challenging environments, we want to hear from youResponsibilities: • Own and drive timing closure for complex SoC and ASIC designs across multiple technology nodes • Performfull-chipand block-level timing analysis using industry-standard tools (Primetime, Tempus, etc.) • Collaborate with RTL, synthesis, physical design, and verification teams to resolve timing violations • Develop and maintaintiming constraints (SDC), run STA checks (setup, hold, DRV, SI), and support ECO timing closure • Contribute to methodology improvements and timing signoff strategies • Report timing status, risks, and closure plans to technical leads and project stakeholdersRequired Skills & Experience: • 5–15 years of solid hands-on experience in STA and timing closure • Strong expertise in timing concepts, constraints development, and signoff methodology • Proficient in tools like Synopsys Primetime, Cadence Tempus • Solid understanding of clock tree design, DFT, multi-mode multi-corner (MMMC) analysis • Good scripting skills (TCL/Perl/Python) to automate and debug flows • Experience with advanced nodes (7nm/5nm/FinFET) is a plus • Strong analytical, problem-solving, and communication skillsWhy Join Wafer Space? • Be part of a high-growth, innovation-driven semiconductor company • Work on state-of-the-art technologies with leading global clients • Collaborative and empowering work culture • Competitive compensation and flexible work options • Opportunity to grow your career in a technically challenging environmentInterested? Send your resume tovaishnavi.suvarna@acldigital.com
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Full Chip STA Lead
7 days ago
New Delhi, India eInfochips (An Arrow Company) Full timeFull Chip STA Lead (8+ Years Experience)Locations:Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, PuneJob Description: We are looking for an experiencedFull Chip STA Leadwith strong expertise in full-chip timing, constraint management, and cross-functional collaboration. The ideal candidate will drive timing closure activities for complex SoCs and provide...
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STA Engineer
1 day ago
New Delhi, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilledSTA / PTPX Engineerswith strong experience in timing sign-off and power analysis. ️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints, ECOs,...
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STA Engineers
5 days ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timeStatic Timing Analysis (STA) Engineer Job SummaryThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...
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STA Engineers
4 weeks ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timeStatic Timing Analysis (STA) EngineerJob Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...
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STA CAD Engineer
3 days ago
New Delhi, India ACL Digital Full timeGreetings from ACL Digital We are looking for STA CAD Engineers.Experience Level:4+ years of STA CAD Job Description: STA CAD Engineer Location: Hyderabad and BangaloreJob Description: Bachelor's degree in Electrical or Computer Engineering and 4+ years STA (Timing, Constrains)/CAD experience or Master's degree and 2+ years' experience • Excellent...
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STA Engineer
2 weeks ago
New Delhi, India ACL Digital Full timeRole:STA Engineer Experience:3+ Years Location:Bangalore (Onsite) Notice Period:Immediate to 30 Days / Serving NoticeKey Responsibilities: PerformStatic Timing Analysis (STA)at block and full-chip levels across multiple design stages (synthesis, P&R, sign-off). Develop, validate, and maintaintiming constraints (SDC files)for complex SoC and IP-level designs....
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Senior STA Architect
2 weeks ago
New Delhi, India Eximietas Design Full timeHello All,Eximietas Design Hiring STA Engineers/LeadsExperience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:- Experience in Static Timing Analysis (STA) for ASIC designs. - Experience in developing timing constraints. - Experience in timing closure and...
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STA CAD Engineer
5 days ago
New Delhi, India ACL Digital Full timeGreetings from ACL DigitalWe are looking for STA CAD Engineers.Experience Level:4+ years of STA CADJob Description: STA CAD EngineerLocation: Hyderabad and BangaloreJob Description:- Bachelor's degree in Electrical or Computer Engineering and 4+ years STA (Timing, Constrains)/CAD experience or Master's degree and 2+ years' experience - • Excellent...
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Full Chip STA Lead
1 week ago
Delhi, India eInfochips (An Arrow Company) Full timeFull Chip STA Lead (8+ Years Experience) Locations: Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, Pune Job Description: We are looking for an experienced Full Chip STA Lead with strong expertise in full-chip timing, constraint management, and cross-functional collaboration. The ideal candidate will drive timing closure activities for complex SoCs and...
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Full Chip STA Lead
7 days ago
Delhi, India eInfochips (An Arrow Company) Full timeFull Chip STA Lead (8+ Years Experience) Locations: Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, Pune Job Description: We are looking for an experienced Full Chip STA Lead with strong expertise in full-chip timing, constraint management, and cross-functional collaboration. The ideal candidate will drive timing closure activities for complex SoCs and...
