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New Delhi, India ACL Digital Full time

RTL FPGA Design Engineer Experience : 2-4 years Location : Hyderabad FPGA architecture Vivado Flow Scripting and automation Verilog / VHDL HW debugging We are looking for some background of scripting and or conceptual understanding of Power for experienced candidates.Interested,please share your updated resume to janagaradha.n@acldigital.com