RTL FPGA Engineer with HAPS prototyping

Job DescriptionRole :RTL FPGA Engineer with HAPS prototyping experience Roles and Responsibilities :Experience: 5-10YrsWork location: Bangalore5–10 years’ hands-on experience with Synopsys HAPS boards and ProtoCompiler/Identify Debug. Strong RTL design/verification skills in Verilog/SystemVerilog.Proven FPGA implementation expertise: synthesis,...

We’re Hiring: RTL FPGA Engineer (HAPS Prototyping)Location: Bangalore | Experience: 5–10 years If you have hands-on experience withSynopsys HAPS boards,ProtoCompiler, andIdentify Debug, we want to hear from you! ✅ Strong RTL design/verification (Verilog/SystemVerilog) ✅ FPGA implementation: synthesis, floorplanning, timing closure ✅ Board-level...

RTL FPGA Engineer with HAPS prototyping experience Experience: 5-10Yrs Work location: BangaloreRoles and Responsibilities: 5–10 years’ hands-on experience with Synopsys HAPS boards and ProtoCompiler/Identify Debug. Strong RTL design/verification skills in Verilog/SystemVerilog. Proven FPGA implementation expertise: synthesis, floorplanning, SDC...

FPGA prototyping Engineer Candidate with 10+ years of experience in FPGA prototyping, who can work independently on the prototyping. Candidate should be able to do modification independently in the verilog models and add/modify glue logic to fit into the FPGA system. Should be able to run simulation in the FPGA test bench to ensure the basic QC checks met...

RTL FPGA Design Engineer Experience : 2-4 years Location : Hyderabad FPGA architecture Vivado Flow Scripting and automation Verilog / VHDL HW debugging We are looking for some background of scripting and or conceptual understanding of Power for experienced candidates.Interested,please share your updated resume to janagaradha.n@acldigital.com

RTL FPGA Design EngineerExperience : 2-4 years Location : Hyderabad FPGA architecture Vivado Flow Scripting and automation Verilog / VHDL HW debugging We are looking for some background of scripting and or conceptual understanding of Power for experienced candidates.Interested,please share your updated resume to janagaradha.n@acldigital.com

Position: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...

Position: RTL Design EngineerExperience: 5 to 8 YearsLocation: Noida & AhmedabadWe are looking for an experienced RTL Design Engineer with strong expertise in Verilog, FPGA design, and Xilinx platforms. The role involves working closely with cross-functional teams to deliver high-performance digital design solutions.Key Responsibilities- Design, develop, and...

About Us We are a dynamic team of young engineers, domain experts, and seasoned sales professionals dedicated to providing comprehensive turnkey solutions for complex challenges in Signal Processing. Our expertise spans the cutting-edge technologies in Signal Processing, addressing critical needs in the Defence and Aerospace sectors. Our offerings encompass...

About UsWe are a dynamic team of young engineers, domain experts, and seasoned sales professionals dedicated to providing comprehensive turnkey solutions for complex challenges in Signal Processing. Our expertise spans the cutting-edge technologies in Signal Processing, addressing critical needs in the Defence and Aerospace sectors. Our offerings encompass a...