Analog layout Engineer

3 weeks ago


New Delhi, India ACL Digital Full time

Exp level: 2 to 5 yearsLocation: BangaloreNotice Period: Immediate joiners are preffered.Responsibilites:- Design and implement analog layouts for high-performance circuits (e.g., amplifiers, ADCs, DACs, voltage regulators) using TSMC 3nm and 5nm nodes. - Perform design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC) to ensure design compliance.Required Skills:- Strong experience in analog layout design at advanced nodes (TSMC 3nm and 5nm). - Proficiency in layout tools like Cadence Virtuoso, Synopsys IC Compiler, or similar. - Understanding of layout-dependent effects (LDE) and its impact on performance. - Knowledge of parasitic extraction, simulation, and optimization. - Familiarity with design for manufacturability (DFM) techniques.Please email Resumes to raksha.k@acldigital.com



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