Senior Analog Layout Engineer

3 weeks ago

New Delhi, India Best NanoTech Full time

Experience: 8+ YearsLocation: Remote / India (must support USA/Canada time zone)Travel: Willing to travel to the U.S. for project release (as required)Role Overview:We are looking for a Senior Analog Layout Engineer to work on a high-speed analog chip development in advanced TSMC 5nm technology. The candidate will operate as an individual contributor, responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision.This role demands deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simulation concepts. The engineer will work closely with SoC, Circuit, and Digital teams to ensure robust layout quality and performance.Key Responsibilities:- Own end-to-end schematic-to-layout design for high-speed analog and mixed-signal circuits. - Perform floor planning, bump and pad-ring design, and ESD implementation at the chip level. - Collaborate with SoC, circuit, and digital design teams for layout integration and signoff. - Ensure layouts meet all DRC, LVS, ERC, EM/IR and reliability standards. - Handle layout matching, shielding, and parasitic optimization for high-speed performance. - Support simulation correlation and assist in debugging layout-related circuit issues. - Work independently, taking full ownership of assigned IPs and layout deliverables.Required Skills and Expertise:- 8+ years of hands-on experience in Analog & Mixed-Signal Layout, focusing on high-speed analog chips (High-Speed Converters). - Proven expertise with TSMC 5nm FinFET technology and advanced layout techniques. - Strong understanding of chip-level planning, bump mapping, and ESD design. - Familiarity with simulation and circuit performance basics (gain, bandwidth, noise, etc.). - Proficiency in Cadence Virtuoso, Calibre, and PVS. - Excellent grasp of symmetry, matching, shielding, and low parasitic layout design. - Ability to work independently and coordinate effectively with global teams. - Flexibility to work in USA/Canada time zones and travel abroad if required.Preferred:- Experience with PCIe & GDDR. - Exposure to Chip-Package Co-Design (CPCD) and advanced ESD methodologies. - Prior experience in product-level high-speed analog chip delivery.

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