Design Verification Engineer
1 month ago
Role : Design Verification
Location : Bangalore, India
Experience : 3-10 Years
Notice Period : Immediate or up to 1 Month
About the Role :
We are seeking an experienced Design Verification specialized in different verification methodologies to join our Research & Development (R&D) team. You will be part of the team verifying IPs and SoCs.
Requirements :
- Hands on project experience with verification methodologies UVM
- Domain experience of PCI-e, AMBA, I3C and DDR protocols
- Hands on project experience in verifying SoC with C-SV/UVM based environments.
- Can understand clocking, reset architecture and data flows. Has knowledge of SoC bring-up, bus protocol, register and address map Verification.
- Experience in coverage/assertion driven verification.
- Good knowledge of UNIX shell scripting, Perl and Python scripting
- Experience in writing verification plans and test bench development, simulation, and debugging.
- Proficient with CAE/CAD tools such as schematic capture, simulation, design verification
- Good analytical and problem-solving skills.
- Verifying RTL implementation for complex digital blocks to ensure high quality
- Developing verification strategies for new features, plan volume validation and coverage strategies
- Writing test plan, developing testbenches, coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM
- Working with designers to do coverage analysis and take necessary actions to meet coverage goals
- Integrate VIPs as needed
- Closely work with design teams to drive feature enablement
- Mentor junior engineers on the team
Preferred Experience :
- Desired experience : 3 years in real time projects
- Working experience on PCIe, DMA and/or NVMe protocols required
- Knowledge of bus protocols like AXI/AHB desired
- Grounds-up development experience with implementation of UVM/OVM and/or Verilog, System Verilog test benches and/or BFMs is required
- Strong understanding of simulation tools and knowledge of scripting languages like Perl, tcl or cshell
- Highly motivated, Self-starter individual with ability to work in a fast-paced team environment
- Experience with verification methodology like OVM/VMM/UVM
- Education Background : BS in EE/CE & 10+ years of experience, or an MS in EE/CE & 7+ years of experience in pre-silicon verification
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