Design Verification Engineer
3 weeks ago
- The role will own verification of one or more IP blocks at IP-level andleading to chip-level for USB and automotive applications.
- The role will be responsible for Testbench Architecture, Test planning,Test Development and Verification for IP Blocks and Subsystems.
- The role will work on verification closure, including test plan,coverage and assertion closure
- The role will Interact with other functional leads from Design, DFT andFW/SW Teams
- The role will evaluate new tools & methodologies required for continuousimprovement of design flows
- Guide & Mentor junior engineers working on IP Blocks
You are best equipped for this task if you have:
- Bachelors/Masters in Electrical/Electronics Engineering with 7-10 yearsof experience
- Thorough understanding of System Verilog & UVM framework for IPVerification
- Thorough understanding of Coverage Driven Verification
- Experience with Assertion Development & ABV
- Experience with Power Aware Verification
- Experience in verification of designs in RTL & GLS
- Experience in maintaining verification architecture for platforms
- Experience of leading a team for IP-level verification
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