Design and verification engineer
3 weeks ago
Define and implement IP/So C verification plans, build verification test benches to enable IP/sub-system/So C level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Qualifications and Skills for DV Positions:
Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience
5+ years of hands-on experience in System Verilog/UVM methodology and/or C/C++ based verification
5+ years experience in IP/sub-system and/or So C level verification based on System Verilog UVM/OVM based methodologies
Experience in development of UVM based verification environments from scratch
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Experience with verification of ARM/RISC-V based CPU sub-systems or So Cs
Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Experience with revision control systems like Mercurial(Hg), Git or SVN
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