Senior Lead STA Physical Design Engineer
4 weeks ago
Your responsibilities may include but not be limited to:
SOC, clock design, and power delivery integration.
Driving performance optimization, including co-optimization work with process teams, to create best-in-class designs.
Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.
Static timing analysis constraint understanding and generation, clock stamping, and timing closure.
Multiple Power Domain analysis using standard Power Formats UPF or CPF.
The ideal candidate should exhibit behavioral traits that indicate:
Self-motivator with strong problem-solving skills.
Excellent interpersonal skills, including written, verbal, and presentation communications
Attention to detail and organizational skills
Ability to work as part of a team and collaborate in a high-paced atmosphere.
Qualifications:
Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.
Static timing analysis constraint understanding and generation, clock stamping, and timing closure.
Multiple Power Domain analysis using standard Power Formats UPF or CPF
Preferred Qualifications:
6-15 years of experience in Physical Design with STA.
Experience with product development and delivery on leading edge process nodes.
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