Lead STA

2 weeks ago


New Delhi, India Cadence System Design and Analysis Full time

BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization techniques.• Participate in IP release to customers and support team on standardize & document learnings.Key Skills: Netlist-GDS physical design, 7nm+ Technology nodes, CTS and Custom Clocking, STA, PV, scripting tcl & python.Minimum qualifications:• Bachelor’s degree in Electronics or equivalent practical experience.• 3+ years of experience and in depth knowledge on Netlist-GDS physical design.• Experience on sub 7nm tech nodes.• Good hands on experience on scripting tcl & python.Preferred qualifications:• Experience in hardening DDR PHY designs.• Experience in physical synthesis and constraints design.• Experience in Cadence tools Innovus, Genus, Tempus & Voltus.• Experience in RDL routing, PERC ESD checks.• Lower Tech node N3, Samsung N5,N4 knowledge is a plus.



  • New Delhi, India ACL Digital Full time

    We’re Hiring: STA Engineer | 5–15 Years Experience | BangaloreCompany:ACL Digital Company Location:Bangalore Experience:5 to 15 Years Job Type:Full-TimeACL Digitalis looking forSenior Static Timing Analysis (STA) Engineerswith solid experience in timing closure of advanced SoC designs. If you’re an STA expert who thrives in fast-paced, technically...

  • Lead STA Engineer

    4 weeks ago


    New Delhi, India Tessolve Full time

    About Us:Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing...

  • Lead STA Engineer

    3 weeks ago


    New Delhi, India Tessolve Full time

    About Us: Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing...

  • Senior STA Architect

    3 weeks ago


    New Delhi, India Eximietas Design Full time

    Hello All,Eximietas Design Hiring STA Engineers/Leads Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US.Job Description: Experience in Static Timing Analysis (STA) for ASIC designs. Experience in developing timing constraints. Experience in timing closure and...


  • New Delhi, India Tenstorrent Full time

    Tenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. Engineers with a strong foundation in Static Timing Analysis (STA) and timing constraints . In this role, you’ll lead timing closure efforts across block and full-chip levels,...


  • New Delhi, India Tenstorrent Full time

    Tenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs.Engineerswith a strong foundation inStatic Timing Analysis (STA)andtiming constraints .In this role, you’ll lead timing closure efforts across block and full-chip levels,...

  • Lead

    3 weeks ago


    New Delhi, India Tessolve Full time

    Job Title: STA Engineer – VLSILocation: BangaloreCompany: TessolveExperience Required: 4+ years-Educational Qualifications: Bachelor's or Master’s degreeJob Description:We are seeking a skilled Static Timing Analysis (STA) Engineer with experience in the VLSI domain. The ideal candidate will be responsible for performing and analyzing timing across...

  • Lead

    4 weeks ago


    New Delhi, India Tessolve Full time

    Job Title: STA Engineer – VLSI Location: Bangalore Company: Tessolve Experience Required: 4+ years Educational Qualifications: Bachelor'sor Master’s degree inElectrical/Electronics Engineering ,VLSI , or related fieldsJob Description: We are seeking a skilledStatic Timing Analysis (STA) Engineerwith experience in the VLSI domain. The ideal candidate will...

  • Lead

    3 weeks ago


    New Delhi, India Tessolve Full time

    Job Title: STA Engineer – VLSI Location: Bangalore Company: Tessolve Experience Required: 4+ years Educational Qualifications: Bachelor'sor Master’s degreeJob Description: We are seeking a skilledStatic Timing Analysis (STA) Engineerwith experience in the VLSI domain. The ideal candidate will be responsible for performing and analyzing timing across...

  • Physical Design Lead

    2 weeks ago


    New Delhi, India L&T Technology Services Full time

    Hello Folks, we at LTTS are looking for Physical design Lead role with 8+ years of experience.Deatiled JD is below as mentioned...Candidates with PnR – 8+ ’ experience• IP/Block level PnR activities from Netlist to GDS-II.• Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV,...