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Formal Verification
3 months ago
Academic/Job Qualifications:Required BE/B.Tech in Electronics and Communication (E&C) or CSEDesired: ME/M.Tech in VLSI or Microelectronics
Work Experience5-10 years in Digital Design/Functional Verification domainIn the past roles, should have served in roles like Application Engineer, Design/Verification engineer, Methodology engineer in handling medium to high complexity ASICs/FPGAs
Technical SkillsStrong hold on VHDL/Verilog and SystemVerilog.RTL and understanding of ASIC design flowsExperience and working knowledge of static (Lint, CDC, RDC, Constraints etc) or Formal (Property checking, SVA, equivalence checking, connectivity, Functional safety etc) or Dynamic verification methodologies (simulation, emulation or prototyping)Simulation/Verification using directed tests, constraint random testing, assertions and coverage driven verification methods; RTL and Gate Level (GLS) verification and debug would be plusExposure to C, python, UVM Strong working knowledge in EDA tools like VCS, VC Formal, VC SpyGlass, Verdi is required.
Soft SkillsResolves issues in creative ways. Exercises autonomous judgment in selecting methods and techniques to obtain solutions.Executes projects from start to completion. Contributes to moderately complex aspects of a projectEstablishes and develops recommendations to solutions. Works on team-driven or task-oriented projects. May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise.Collaborates with customers and publicises creative work and innovative solutions in forums such as SNUG, DVCon etc