Senior Physical Design Engineer

Experience: 3 - 6 YearsNotice period: ImmediateLocation: Bangalore & HyderabadResponsibilitiesMandatory Experience in Full Chip Timing.Strong background in digital IC design, including floorplanning, placement, routing, clock tree synthesis, and optimization.Tools Expertise: Proficient in Innovus, ICC2, and Fusion Compiler for place and route, timing...

• PNR Leads Required with Shorter Notice period to lead a Team for a Long-Term Project.• Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. • Experience in PnR tools like ICC/Innovus with regards to physical convergence must. • Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV. • Good overall...

Should be able to handle Full chip hashtagAdded advantage for #Innovus with Minimum 4 years #PnR (timing/congestion/CTS issues), understanding of hashtag#IO ring,#package support, multi hashtag#voltage design.Deep understanding of the concepts related to hashtag#synthesis, place & route, hashtag#CTS, timing convergence, IR/EM checks and signoff DRC/LVS...

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