Full Chip Physical Design Lead

Full Chip STA Lead (8+ Years Experience)Locations: Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, PuneJob Description: We are looking for an experienced Full Chip STA Lead with strong expertise in full-chip timing, constraint management, and cross-functional collaboration. The ideal candidate will drive timing closure activities for complex SoCs and...

Should be able to handle Full chip hashtagAdded advantage for #Innovus with Minimum 4 years #PnR (timing/congestion/CTS issues), understanding of hashtag#IO ring,#package support, multi hashtag#voltage design.Deep understanding of the concepts related to hashtag#synthesis, place & route, hashtag#CTS, timing convergence, IR/EM checks and signoff DRC/LVS...

Technical RequirementsExcellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team.In-depth knowledge of floor planning, power planning, PNR and signoff checksStrong experience in static timing analysis (STA), timing closure, and signal integrity.Expertise in power optimization...

Experience: 3 - 6 YearsNotice period: ImmediateLocation: Bangalore & HyderabadResponsibilitiesMandatory Experience in Full Chip Timing.Strong background in digital IC design, including floorplanning, placement, routing, clock tree synthesis, and optimization.Tools Expertise: Proficient in Innovus, ICC2, and Fusion Compiler for place and route, timing...

Director- Physical DesignAbout SemifiveFounded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions....

PHYSICAL DESIGN ENGINEER/LEAD - NOIDA/Ahmedabad/Bangalore/Hyderabad/Pune(NO WORK FROM HOME OR REMOTE WORK) Job description: 4 to 15 Years of Hands on ExperienceBlock level Physical Design Implementation from RTL to GDSII or Netlist to GDSII,Block level Physical Signoff,Block level Timing Signoff and ECO generation.Block level Power signoff.Good skill on...

Role: PD LeadExperience: 7+yrsLocation: BangaloreTechnical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for...

Proxelera is India’s premium chip and system software product engineering partner. Our engineers take extreme passion in your assignments and deliver through their years of high quality experience to make your product successful. We understand the challenges of all aspects of product engineering – right from design planning stage to post silicon work. We...

Proxelera is India’s premium chip and system software product engineering partner. Our engineers take extreme passion in your assignments and deliver through their years of high quality experience to make your product successful. We understand the challenges of all aspects of product engineering – right from design planning stage to post silicon work. We...

• PNR Leads Required with Shorter Notice period to lead a Team for a Long-Term Project.• Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. • Experience in PnR tools like ICC/Innovus with regards to physical convergence must. • Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV. • Good overall...