Associate Staff Engineer- SoC/ Chip Design
2 weeks ago
We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.
We are Silicon Labs. We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.
What we're looking for:
Job Description
This position involves the development of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, AI accelerators, interconnects, memory architecture and multi-level caches, multiple clocks and resets, high-speed interfaces, peripherals. The chosen candidate would need to contribute to, and manage a team for, the development of architecture, microarchitecture, and design of SoCs which include RISC-V, ARM or proprietary processor designs, and high-speed interfaces for off-chip memories, along with the integration of wireless systems, power management, and mixed signal IP. The candidate would be responsible for the leading a project through the entire product development process.
Responsibilities
Lead the development and execution of Wireless SoC's from definition, through execution, and into production Definition and Planning Coordinate with the product marketing teams to develop the SoC requirements. Provide the necessary design collateral to support the product approval gates. Develop and maintain the SoC architecture or technical specification to meet the product requirements, with a key goal to maximize IP reuse. Develop the design schedule, including milestones and resource requirements. Coordinate with cross functional teams (such as software) on dependencies. Project Execution Coordinate with global design functional leads (RF, baseband, verification, etc) to track execution, triage issues, and perform prudent escalation. Represent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure. Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross functional teams. Follow established quality procedures and processes to achieve first tapeout. Validation to Production Actively support the validation and product test teams during silicon bringup, validation, characterization, and qualification. Triage, track, and resolve issues reported during silicon evaluation. Execute a metal or full layer revision, if necessaryExperience Level: 10+ years in Industry
Education Requirements: Bachelor or Master's degree in Electrical or Computer Engineering
Qualifications:
Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus. Top-down planning and execution of SOC projects. Experience in full-chip development cycle Able to build strong technical team. Hands-on experience in architecture, micro-architecture, digital design processes Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc. Knowledge of processors like RISC-V and ARM processors Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure Knowledge of DFT including Scan, ATPG, MBIST Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) Knowledge of hardware accelerators Knowledge of Verilog and System Verilog Knowledge of scripting languages like Perl, Python, Tcl, shellBenefits & Perks:
Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.
Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support-
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