Senior/Staff CAD Engineer Synthesis

2 weeks ago

Hyderabad, Telangana, India Micron Full time
Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

JR51602 Senior/Staff CAD Engineer Synthesis

Our vision is to transform how the world uses information to enrich life.

Join an inclusive team focused on one thing:
using their expertise in the relentless pursuit of innovation for customers and partners. The solution we create help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while contributing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing.

Job Description:


As a CAD Applications Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for Synthesis flows.

You will work closely with the Design teams to increase their productivity and work efficiency.
Skills Required

:5-8 years of relevant experience in SynthesisGood understanding of overall design Flow RTL to GDS.Experience on signing off the full chip synthesis for tape outsHands on Experience on Constraints Generation, Management for hierarchical designs.
Thorough Understanding of DFT Constraints.
Hand on Synthesis Experience on Lower node Technologies with Synopsys/Cadence Tools. Hands on with TSMC process will be a plus.
Hands on Experience on Equivalent Checks with Synopsys / Cadence Tools.
Good knowledge on Timing Budgets.
Knowledge on Perl / TCL / Python scripting language is a must.
Experience on multi voltage designs using CPF/UPF.Good understanding of the Chip Interface Constraint Generation & Timing Closure.
Hands on experience on power analysis using PTPXGood understanding of VHDL / Verilog Constructs.

Responsibilities:


Responsible for Block/ Chip Tile Synthesis to achieve the best PPA.Constraint Generation & Maintenance for Block / SOC for complex hierarchical Designs for all the Modes.

Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts .Able to work on low power Intent & verify low power intent with minimal supervision.

Responsible for Logical equivalence checks & Low Power Checks.
Early RTL analysis for Clocking, Power , DFT coverage & suggestions to Designer on the improvements.
Support Verification team to enable GLS.

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