Design Verification Lead
1 week ago
Areyou an experienced RTL Verification professional looking for yournext challenge Look nofurther
Qualifications:
- BE/ME/MTech/MSin Electrical Engineering
- 6 to 12 years of RTLverification experience for the Senior RTL Verification Leadposition
- 4 to 5 years of relevant industryexperience for the RTL Verification Engineerposition
- Proficiency in advanced verificationmethodologies like UVM/OVM/VMM/SystemVerilog
- Experience in constrained randomstimulus generation assertionbased verification and functionalcoverage techniques.
- Knowledge of registerverification standards NLP/GLS verificationflows
- Strong experience in IP level andsubsystem level verification on protocols such as PCIE UCIe HBMetc.
- Relevant experience in enabling andverifying controller interoperability testing at the subsystemlevel is aplus
- Leada highly motivated verification team responsible for DV for IPslike UCIe HBM PCIe Bus logic etc. (Senior RTL VerificationLead)
- Implement advanced verificationmethodologies such as UVM/OVM/VMM/SystemVerilog
- Generate constrained random stimulusand perform assertionbased verification.
- Ensurefunctional coverage techniques are appliedeffectively.
- Apply register verificationstandards and NLP/GLS verificationflows.
- Conduct IP level and subsystem levelverification on protocols like PCIE UCIe HBMetc.
- Enable and verify controllerinteroperability testing at the subsystemlevel.
- 6to 12 years of RTL verification experience for the Senior RTLVerification Lead position
- 4 to 5 years ofrelevant industry experience for the RTL Verification Engineerposition
#RTLVerification#SeniorRTLVerificationLead #ASICDesign #VerificationMethodologies#PCIe #UCIe #HBM #JobOpportunity #HiringNow#JoinOurTeam
rtlverification,ip,verilog,universal verification methodology(uvm),vmm
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Design Verification Lead
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