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PCIe Design Verification Lead
4 months ago
Hope youre doing well
We are hiring for the PCIe DesignVerification Lead role. Please find the JDbelow
JOB Designation:PCIe Design Verification Lead
JOB Location: PAN India
Mode of Hiring:Full time FTE
Notice Period: Immediate to 60days
Experience:7 years
Required Skills:
- 7 years of experience in design verificationwith a focus on PCIe protocol.
- Deepunderstanding of PCIe specifications and protocols including PCIeGen3/Gen4/Gen5.
- Proficiency in verificationlanguages such as System Verilog and methodologies likeUVM.
- Experience with industrystandardsimulation tools and environments (e.g. Cadence Incisive SynopsysVCS).
- Strong leadership skills with theability to lead and mentor a team of verificationengineers.
- Excellent communication andinterpersonal skills with the ability to collaborate effectivelywith crossfunctional teams.
- Experience withscripting languages (e.g. Python Perl) for automation is aplus.
- Familiarity with advanced verificationtechniques such as formal verification assertionbased verificationand emulation is desirable.
If anyone is interested please send anupdated CV to