DV- PCIE Verification Engineer

We require 1.DV-Formal verification with must Jasper Gold Exp Exp : 5+Location : BLR/Pune2. DV- WIFI/ Wireless / BT with Test case Dev/debuggingExp : 5+Location : BLR/Pune3. DV- PCIE with Test case Dev/debuggingExp : 5+Location : BLR/Pune

Job Location: Bangalore/ Hyderabad Notice Period: 15 days to 30 Days Minimum: 4 Years Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: DDR,PCIE,USB,MIPI, PCIE Preferred Experience: Should have worked on Processor based System or...

Job Location: Bangalore/ HyderabadNotice Period: 15 days to 30 DaysMinimum: 4 YearsKey Responsibilities:Developing test plansCoding and bring up of asm, c++ testsUVM test bench components coding and maintainingDebugging regression failsProtocol: DDR,PCIE,USB,MIPI, PCIEPreferred Experience:Should have worked on Processor based System or Sub-system level...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience.Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verificationDevelop functional tests based on verification test planDrive Design...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

PCIe Verification Engineer">As a PCIe Verification Engineer, you will be responsible for leading the verification of PCIe interface designs, ensuring compliance with PCIe protocol standards (e.g. PCIe Gen 3/4/5/6, USB3, etc.). You will develop and implement scalable, reusable, and efficient testbenches for PCIe designs using SystemVerilog, UVM (Universal...

Job Opportunity: We are seeking a seasoned Verification Engineer to lead the verification of PCIe interface designs, ensuring compliance with industry-standard protocols.Key Responsibilities:Create and implement scalable, reusable, and efficient testbenches for PCIe designs using SystemVerilog and UVM methodologies.Develop detailed verification plans for...

Job OverviewWe are seeking an experienced Verification Engineer to join our team. The ideal candidate will have a strong background in verification methodologies and System Verilog programming skills.Key Responsibilities:Develop comprehensive verification plans for PCIe IP and Subsystem.Create and maintain testbenches, test cases, and verification...