Senior DV Engineer

Role : DV Senior EngineerExperience : 5–9 years of experienceWork location: BangaloreWork mode: Work from officeInterview process: 1 HR round , 2 Technical roundShould be open for virtual and face to face interview as required by the clientResponsibilities:Implement and debug DV environments and stimuli.Analyze coverage and contribute to test plan...

We require 1.DV-Formal verification with must Jasper Gold Exp Exp : 5+Location : BLR/Pune2. DV- WIFI/ Wireless / BT with Test case Dev/debuggingExp : 5+Location : BLR/Pune3. DV- PCIE with Test case Dev/debuggingExp : 5+Location : BLR/Pune

We are hiring DV Contract Engineers with 10+ years of experience in UVM-based testbenches, netlist/gate-level simulations, and datapath blocks. Strong expertise in Cadence tools (Xcelium/Simvision) and scripting (Python/Shell) required. Required Candidate profileExperienced DV engineer with 10+ years in verification, UVM testbench, Cadence tools...

Responsibilities: Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience.Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verificationDevelop functional tests based on verification test planDrive Design...

Company DescriptionTechsoc Technologies Private Limited is an engineering services company specializing in VLSI design and verification services. Founded by Dudam Rajanikanth, the company has expertise in casting product ideas into System-on-chip with cost effectiveness, optimized performance, and area efficiency. TechsoC caters to the needs of clients...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

LTTS IndiaBangaloreJob DescriptionA DV Engineer, or Design Verification Engineer, is responsible for ensuring the functionality, performance, and reliability of hardware designs, particularly in complex systems like ASICs and SoCs. They work closely with design teams to test designs at various levels, from RTL to full system, and develop test environments to...