DV Engineer

Role:Design Verification EngineerSkill: DV with GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV-IP with Ethernet/PCIENP: Immediate to 30 daysLoc: HYDExp: 10+ yrsRole:Design Verification EngineerSkill: DV with Soc, GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV with...

Role:Design Verification EngineerSkill: DV with GLS ExpNP: Immediate to 30 daysLoc: HYDExp: 3+ yrsRole: Design Verification EngineerSkill: DV with Soc, Arm ProcessorNP: Immediate to 30 daysLoc: BLRExp: 6+ yrs

We are hiring DV Contract Engineers with 10+ years of experience in UVM-based testbenches, netlist/gate-level simulations, and datapath blocks. Strong expertise in Cadence tools (Xcelium/Simvision) and scripting (Python/Shell) required. Required Candidate profileExperienced DV engineer with 10+ years in verification, UVM testbench, Cadence tools...

Role : DV Senior EngineerExperience : 5–9 years of experienceWork location: BangaloreWork mode: Work from officeInterview process: 1 HR round , 2 Technical roundShould be open for virtual and face to face interview as required by the clientResponsibilities:Implement and debug DV environments and stimuli.Analyze coverage and contribute to test plan...

Responsibilities: Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, IndiaDetailed JD is as below ::Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design...

LTTS IndiaBangaloreJob DescriptionA DV Engineer, or Design Verification Engineer, is responsible for ensuring the functionality, performance, and reliability of hardware designs, particularly in complex systems like ASICs and SoCs. They work closely with design teams to test designs at various levels, from RTL to full system, and develop test environments to...

We are hiring a DV Power Management Engineer with 4+ years of experience in PL design, Vivado project flows, and Xilinx/AMD devices. Must be skilled in Linux and scripting (TCL/Shell/Python). Knowledge of RTL coding and Vitis flows is an advantage. Required Candidate profileSeeking a DV Power Management Engineer with 4+ years in PL design, Vivado, and...

General Summary:QCT's Bangalore Wireless R&D(WRD) HW team in Bangalore is looking for experienced Wireless HW design verification engineers to work on Qualcomms best in class chipsets for mobile phones, wearables and IOT . Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work...

Designation- DV – Practice HeadKey ResponsibilitiesLead and scale the Design Verification (DV) practice by building high-performing teams and driving technical excellence.Define and implement advanced verification strategies, methodologies, and best practices for complex SoC, FPGA, and ASIC projects.Collaborate with architecture, design, and product teams...