Verification Lead

1 day ago


Bangalore Urban, India Cyient Full time

Verification Lead / Technical Manager

Location: Bangalore / Hyderabad

Exp: 12 to 20 yrs.


Looking for an experienced senior verification engineer with 12+ years of experience in ASIC/SOC/IP/block level functional verification using system Verilog/UVM.

The ideal candidate will have strong command of UVM, advanced UVM and system verilog


Key responsibilities:

Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM

possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB and Automative

Strong debugging skills to address TB issues quickly and test failures.

Take responsibility for verification closure by addressing coverage and managing bug reports

proficiency in using industry standard verification tools such as Questa, VCS or ModelSim

Experience with scripting languages like python, perl or TCL for automation tasks

Manage a team of 6 to 7 Engineers, Interact with the customer on the tasks and status updates


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