Design Verification Engineer
8 months ago
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Design Verification Engineer (RISCV)
Key Responsibilities:
Define verification plans and develop DV environments independently in System Verilog (SV)/UVM and SV/C.
Create and execute test plans to ensure the quality and reliability of our IP solutions.
Demonstrate expertise in System Verilog and UVM methodologies.
Perform functional verification at the RTL level, including coverage analysis and improvement.
Develop Universal Verification Components (UVCs) from scratch.
Experience working on IPs, with a preference for those with DFD IP experience.
Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field with 5+ years of experience
Proven experience in DV and verification methodologies.
Strong proficiency in System Verilog and UVM.
Ability to work independently and drive projects to completion.
Experience in IP development, particularly in DFD IP, is desirable.
Excellent problem-solving and communication skills.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
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