SRAM Memory Layout Engineer

Job Location: Bangalore Notice Period: Immediate or 15 days Exp:3+ years Responsible for Memory Compiler layout development and verification. · Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. · Perform layout verification like LVS/ DRC/ Latchup,...

Job Location: BangaloreNotice Period: Immediate or 15 daysExp:3+ yearsResponsible for Memory Compiler layout development and verification. · Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. · Perform layout verification like LVS/ DRC/ Latchup, quality...

Job Location: Bangalore Notice Period: Immediate or 15 days Exp:3+ years Responsible for Memory Compiler layout development and verification. · Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. · Perform layout verification like LVS/ DRC/ Latchup,...

Job Location: BangaloreNotice Period: Immediate or 15 daysExp:3+ yearsResponsible for Memory Compiler layout development and verification. · Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. · Perform layout verification like LVS/ DRC/ Latchup, quality...

**Company**: Qualcomm India Private Limited **Job Area**: Engineering Services Group, Engineering Services Group > Layout Engineer **General Summary**: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout...

Team: End to end SRAM design for Mediatek’s processors (CPU, GPU, AI) - SRAM Design, Layout, Qualification, Release, Silicon validationQualification: ·Required Experience : 5 – 8 Years·Degree : ME/M.Tech in Electronic Engineering R&R: ·Working with the SRAM team responsible for FCI design for xCPU systems from R2G.·Collaborate with CPU/GPU/APU team...

Team: End to end SRAM design for Mediatek’s processors (CPU, GPU, AI) - SRAM Design, Layout, Qualification, Release, Silicon validation Qualification: ·Required Experience : 5 – 8 Years ·Degree : ME/M.Tech in Electronic Engineering R&R: ·Working with the SRAM team responsible for FCI design for xCPU systems from R2G. ·Collaborate with...

Team: End to end SRAM design for Mediatek’s processors (CPU, GPU, AI) - SRAM Design, Layout, Qualification, Release, Silicon validationQualification: ·Required Experience : 5 – 8 Years·Degree : ME/M.Tech in Electronic Engineering R&R: ·Working with the SRAM team responsible for FCI design for xCPU systems from R2G.·Collaborate with CPU/GPU/APU team...

**Title**:Memory IP Design - **(MTPM/OTP/MRAM/SRAM/eFlash)** **About **GlobalFoundries** **Introduction**: **Your Job**: - Circuit design, simulation, and characterization of full custom circuits - Functional simulations and statistical analysis - Sign off and release the memory IP’s on dedicated IP validation test chips - Support Silicon bring-up and...

**Title**:Intern - Memory Design **About GlobalFoundries** **Introduction** Bangalore GlobalFoundries (GF) Bangalore is seeking a highly skilled and motivated semiconductor development engineer for an internship position. The student will work for embedded memory development in GF Bangalore **Your Job** - Circuit Design and...

Memory Layout Experience: 4 to 6 yearsSkills required:- Hands-on Experience in top level memory Layout.- Technode experience from 28nm -3nm- Experience Using Cadence Virtuoso Layout Editor, Mentor Graphics Calibre, Verification Tool- Performing various kinds of layouts, implementations from top-level, floor planning down to complex block level layouts.-...

Memory Layout Experience: 4 to 6 yearsSkills required:Hands-on Experience in top level memory Layout.Technode experience from 28nm -3nmExperience Using Cadence Virtuoso Layout Editor, Mentor Graphics Calibre, Verification ToolPerforming various kinds of layouts, implementations from top-level, floor planning down to complex block level layouts.Knowledge of...

Memory Layout Experience: 4 to 6 years Skills required:Hands-on Experience in top level memory Layout.Technode experience from 28nm -3nmExperience Using Cadence Virtuoso Layout Editor, Mentor Graphics Calibre, Verification ToolPerforming various kinds of layouts, implementations from top-level, floor planning down to complex block level layouts.Knowledge of...

We are now looking for a CAD Layout Design Engineer!NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a...

Analog Devices Foundation IP group is seeking an experiencedSenior Circuit Design Engineer to develop logic IPs (standard cells and memories) to support analog, digital and mixed-signal SOC designs at various technology nodes. Responsibilities would include, but are not limited to: Support internal and external memory compilers. Memory instance view...

Position: Senior Memory Design EngineerLocation: Bangalore / NoidaResponsibilities:As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.Required Skills and Experience :- Understanding of computer architecture and concepts.- Basic understanding of CMOS...

We are now looking for a Senior Circuit Design Engineer! This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have created a team of exceptional people stretching around the globe, whose...

# 1. Memory layout - Sr. Engineer / LeadBengaluru, IndiaExperience: 4-8 YrsSkills required:•Hands-on Experience in top level memory Layout.•Technode experience from 28nm -3nm•Experience Using Cadence Virtuoso Layout Editor, Mentor Graphics Calibre, Verification Tool•Performing various kinds of layouts, implementations from top-level, floor planning...

# 1. Memory layout - Sr. Engineer / LeadBengaluru, IndiaExperience: 4-8 YrsSkills required:•Hands-on Experience in top level memory Layout.•Technode experience from 28nm -3nm•Experience Using Cadence Virtuoso Layout Editor, Mentor Graphics Calibre, Verification Tool•Performing various kinds of layouts, implementations from top-level, floor planning...

# 1. Memory layout - Sr. Engineer / LeadBengaluru, IndiaExperience: 4-8 YrsSkills required:•      Hands-on Experience in top level memory Layout.•      Technode experience from 28nm -3nm•      Experience Using Cadence Virtuoso Layout Editor, Mentor Graphics Calibre, Verification Tool•      Performing various kinds of layouts,...