Senior Memory Design Engineer
4 weeks ago
Analog Devices Foundation IP group is seeking an experiencedSenior Circuit Design Engineer to develop logic IPs (standard cells and memories) to support analog, digital and mixed-signal SOC designs at various technology nodes.
Responsibilities would include, but are not limited to:
Support internal and external memory compilers.
Memory instance view generation and characterization.
Memory development andbitcell analysis.
Develop memory verification methodology.
Post silicon memory analysis
Conducting PPA benchmarking exercise for process selection
Drive technical requirements, feasibility analysis, benchmarking exercises and recommendation to provide technical advantage to ADI’s product portfolio.
Work closely with external agencies (library vendors, foundry partners) to define, execute and supervise specific memory development activities.
Minimum Requirements:
Master's degree in Electrical Engineering or equivalent with 3+ years of related experience in logic IP development
Strong knowledge on circuit design and transistor-level/gate-level simulations
Strong experience in design, characterization, and verification of custom memory circuits such as SRAM, Register Files, ROM, MRAM, etc
Experience in physical design methods on memory peripheral circuit or other custom circuits
Strong understanding in process technology including FinFET processes.
Experience with EDA Tools for design, layout and simulation
Strong foundation with analog and digital design flows.
Experience in programming or scripting
Strong written and verbal communication skills
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days-
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Bengaluru, India Analog Devices Full timeAnalog Devices Foundation IP group is seeking an experiencedSenior Circuit Design Engineer to develop logic IPs (standard cells and memories) to support analog, digital and mixed-signal SOC designs at various technology nodes.Responsibilities would include, but are not limited to:Support internal and external memory compilers.Memory instance view generation...
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