IO Layout Design Engineer

1 month ago

Bengaluru, India UST Full time

Job Description: IO Layout Engineer


Company Overview:

UST Global is a leading digital technology solutions company dedicated to transforming businesses through innovation. With a presence in over 25 countries, we provide cutting-edge solutions in areas such as digital consulting, automation, product engineering, and cloud computing. Our mission is to deliver tangible impact and value to our clients, making technology accessible and impactful for all.


Position Overview:

UST Global is seeking an experienced IO Layout Engineer to join our team. The ideal candidate will have hands-on expertise in IO block-level and module-level layout design, as well as experience with FinFET technologies and advanced verification platforms. This role will involve designing, developing, and verifying IO blocks, with a focus on reliability and manufacturability.


Key Responsibilities:

IO Layout Design:

- Perform block-level and full-module IO layout design with attention to detail and layout optimization.

- Develop IOs from scratch, including floor planning, power bus design, ESD (Electrostatic Discharge) protection, and PAD cell integration.


Verification and Compliance:

- Utilize Calibre and PVS (Physical Verification System) platforms to perform DRC (Design Rule Check), LVS (Layout Versus Schematic), and other verification processes to ensure design compliance.


Knowledge of IC Fabrication and Reliability:

- Apply strong knowledge of IC fabrication processes, layout design fundamentals, and best practices to mitigate reliability issues.


IO Knowledge and FinFET Technology:

- Bring expertise in IO fundamentals and different IO types, especially with experience in FinFET technologies.


Qualifications:

- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.

- 5+ years of experience in IO layout design, with a focus on block-level and full-module design.

- Proven experience in developing IOs from scratch, including floor planning, power bus design, ESD protection, and PAD cell layout.

- Hands-on experience with Calibre and PVS verification platforms.

- Solid understanding of IC fabrication processes, layout design fundamentals, and IO reliability issues.

- Familiarity with FinFET technologies is highly preferred.


Preferred Skills:

- Strong analytical and problem-solving skills.

- Ability to work effectively in a team and communicate clearly with cross-functional teams.

- Experience with advanced layout challenges and DFM (Design for Manufacturability) considerations.


Why Join UST Global?

At UST Global, we offer a collaborative and innovative work environment with opportunities for professional growth. As part of our team, you’ll work on pioneering projects that make a meaningful impact in technology, helping us build solutions that shape the future.


If you are passionate about layout design and meet the qualifications, we encourage you to apply.

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