IO Pad Layout Engineer: Expert Design Position for In-Person Work
2 weeks ago
Company Overview
DigiNhance pvt ltd is a dynamic company that specializes in IO layout design. We are seeking an experienced engineer to join our team and contribute to the development of innovative IO layouts.
Estimated Salary Range
The estimated salary range for this position is between $90,000 and $120,000 per annum, depending on experience and qualifications.
Job Description
We are looking for an IO pad layout engineer with 2+ years of experience in designing and implementing IO layouts for Bulk CMOS and FINFET nodes. The ideal candidate will have expertise in using industry-standard tools such as Cadence Virtuoso and Calibre. Experience in working on ESD layouts, handling antenna/EM issues, and independently debugging layout issues is also essential.
Key Responsibilities
- Design and implement high-quality IO layouts for Bulk CMOS and FINFET nodes.
- Utilize industry-standard tools such as Cadence Virtuoso and Calibre to optimize IO layouts.
- Work closely with cross-functional teams to ensure seamless implementation of ESD layouts and handling of antenna/EM issues.
- Independently debug and resolve layout issues in a timely manner.
Requirements
- Good knowledge of GPIO blocks, transmitters, receivers, and other relevant technologies.
- Experience in working with CMOS logic and related concepts.
- Expertise in using industry-standard tools such as Cadence Virtuoso and Calibre.
- Ability to work independently and collaboratively as part of a team.
Benefits
- Ongoing training and professional development opportunities.
- Competitive salary and benefits package.
- A collaborative and dynamic work environment.
Other Requirements
- Good understanding of scripting languages such as SKILL or other similar programming languages.
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Bengaluru, Karnataka, India DigiNhance pvt ltd Full timeAbout the RoleDigiNhance pvt ltd is seeking an experienced IO Pad Layout Engineer to join our team. This role involves designing and implementing high-quality IO layouts for Bulk CMOS and FINFET nodes.As an IO Pad Layout Engineer, you will be responsible for working on complex IO layout designs, ensuring compliance with industry standards and best practices....
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