PCIe-CXL-Senior Principal Micro-Architect
3 weeks ago
PCIe-CXL-Senior Principal Micro-Architect / Principal Architect
a well-funded start-up, founded by serial entrepreneurs and seasoned industry veterans, that is developing a family of best-in-class, high-performance Intelligent Data platforms for the emerging AI/ML applications. A new revolutionary data platform that is optimized for both on-prem and cloud infrastructures.
Experience: 12-25 years
Location: Bengaluru, India
Job Type: Full Time
Description:
- Principal RTL Design Engineer with experience in Architecting/designing/integrating PCIe Root Complex, Host Bridge, Root Port, Address Translation Service and IOMMU for Server side PCIe Root Complex functionality.
- Ability to use IPs from standard vendors and Architect/Design any additional logic modules to be able to integrate with rest of the ASIC modules in the Server SoC ASICs.
- A thorough understanding of System level functionality and how PCIe/CXL Root Complex modules integrate with Cache-Coherent NoCs, Memory Subsystems, CPU complexes through AMBA bus protocols is required.
- Also, need to design and integrate CXL.io and CXL.mem functionality into the Root Complex and Root Port Modules by configuring the IPs from Standard Vendors like Synopsys.
- Work with our design and verification teams spread across Armenia, India, China, and the backend/PR team located in China.
Contact
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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