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Senior Principal FPGA Architect
3 weeks ago
Senior Principal FPGA Architect
Location: Bangalore
Job Description:
Ø As a Senior Principal Engineer/Architect will be working on our existing and next generation Protocol Analysers and similar products.
Ø Opportunity to develop a new product to top 10 semiconductor companies to test their next generation products
Ø The role involves contributing to the entire FPGA based product development flow starting from requirement analysis till final product testing in lab environment.
Ø The candidate will be responsible for architecture/micro-architecture design and implementation of the logic in Verilog for targeted FPGA, writing test benches to validate the design etc.
Ø Job involves working with team of FPGA Design Engineers and deliver the products as planned
Ø Debugging of designs to resolve complex design issues.
Ø Job involves frequent interaction with board design, software, testing and lab teams to deliver the product meeting the customer requirements.
Ø Job involves understanding and working with interfaces such as PCIe, GigE, MPHY/UFS, DPHY/CSI/DSI, USB, SD, eMMC, I3C/I2C, SPI/QSPI etc.
Ø Contributing to/participating in internal design reviews to ensure adherence to the company FPGA design process.
Ø Participate and Contribute to the standard bodies such as PCieSig, MIPI Alliance, SD Association and USB Org
Ø Owns responsibility filing patents.
Ø Individual Contributor Role
Qualifications:
Ø BE/ME in Electronics from a reputed college. Specialization in VLSI and Embedded Design is a plus.
Ø 15 to 20 years of experience in designing and implementing FPGA based solution in Xilinx or Altera FPGA, preferably FPGA based product development experience.
Ø Must have experience in System Design with Xilinx/Altera FPGA devices with relevant tools.
Ø Must have experience in Verilog and/or VHDL coding.
Ø Must have very good understanding of physical layer of SERDES of XILINX-AMD or Intel FPGA
Ø Must deep Knowledge of PCIe, NVME and CXL protocols
Ø Must have experience in synthesis and implementation (floor planning and placement and routing) using FPGA tools.
Ø Must have experience in using constraints to achieve timing requirement.
Ø Experience in working on high speed FPGA designs is a major plus.
Ø Thorough knowledge of Static Timing Analysis (STA) is an added advantage.
Ø Must have experience in building test bench for verification.
Ø Must have experience in board level testing and system debugging.
Ø Preferably candidate should have experience IP development of PCIeGen5/6, DP, CSI and DSI
Ø Must have hands on experience with FPGA debugging tools and test & measurement instruments such as oscilloscope and Logic Analyzer.
Ø Should have strong problem solving and debugging skills.
Designation: Senior Principal Engineer
Contact
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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