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Design Verification Engineer
4 months ago
Responsibilities
Exp : Min 4+ years
- Hands On Experience, in IP/SOC Verification
- Have Experience of one or more Project Cycles including Tape Outs
- Design & Verification Failure Debugging Skills
- Verilog, System Verilog, & UVM Testbench Coding
- Functional Coverage Development, & Coverage Closure
- Assertion/Checker Development
- Testcase Planning & Development
- Practical Knowledge of Protocols like: PCIe, Ethernet, CXL, USB, CAN, LIN, FlexRay, AXI, AHB, APB
- Concepts in Digital Design
- Problem Solving & Analytical Skills
Qualifications : BTECH/MTECH